1. Field of the Disclosure
The disclosure relates generally to memory devices, and, more particularly, to a method for tuning control signals in the memory devices.
2. Description of the Related Art
Generally, processing devices, such as computers, image processing devices, and the like utilize different type of memory devices for storing information, data, firmware and the like, therein. Conventional processing devices may utilize different types of memory devices, such as a Synchronous Dynamic Random Access Memory (SDRAM), a flash memory, a Read Only Memory (ROM), and the like depending upon specific operations such memory devices are intended to perform. An SDRAM is a volatile memory device that is based on a synchronous timing platform. Specifically, the SDRAM is adapted to respond to control signals and transfer data in synchronization with a clock signal of a driving circuit, such as a memory controller, interfaced thereto. Typically, the SDRAM may be a Single Data Rate SDRAM or a Double Data Rate (DDR) SDRAM. The SDR SDRAM is adapted to transfer data on a rising edge of each clock signal while the DDR SDRAM is adapted to transfer data on both a rising and a falling edge of each clock signal thereby achieving double data rate as compared to the SDR SDRAM. In a typical SDRAM system, a plurality of SDRAMs are interfaced to a driving circuit, such as a memory controller that may be implemented in an Application Specific integrated Chip (ASIC). The driving circuit is adapted to perform a number of memory access operations, such as a READ operation and a WRITE operation, for exchanging data with the plurality of SDRAMs.
In such typical SDRAM systems, a timing specification of each SDRAM is required to be met for error-free data exchange between each SDRAM and the driving circuit. If the timing specifications are not met, information being retrieved from or transferred to the SDRAM may include errors, which is highly undesirable in advanced processing systems, such as a parallel processing system, a real-time embedded system, and the like. Also, with increase in clock speeds utilized in driving circuits, the requirement for meeting the timing specification of SDRAMs is essential. Moreover, most of the typical SDRAM systems utilize a large number of SDRAMs. Accordingly, timing requirements for all of the SDRAMs of the SDRAM system are required to be met for preventing errors in the information being exchanged with the SDRAMs.
Generally, in SDRAMs the timing requirement may be met by suitably delaying data being exchanged with respect to the clock signal of the driving circuit. For example, a typical DDR SDRAM utilizes a control signal, such as a DQS signal for enabling exchange of data (in form of “data signals”) between the DDR SDRAM and a driving circuit thereof. Specifically, the DQS signal is generated by the driving circuit during a WRITE operation on the DDR SDRAM. Alternatively, the DQS signal is generated by the DDR SDRAM during a READ operation thereon. During the READ operation, the DDR SDRAM generates the data signal along with the DQS signal in a manner such that the DQS signal is edge-aligned with the data signal. For meeting the timing requirements of the DDR SDRAM during the READ operation, the driving circuit may delay the DQS signal such that the DQS signal is 90 degrees out of phase with the data signal. Specifically, the DQS signal may be aligned at a center of the data signal. Similarly, for meeting timing requirement in SDR SDRAMs, an appropriately delayed clock signal of the driving circuit is utilized such that the data exchanged between the SDR SDRAMs and the driving circuit is error-free. The appropriately delayed clock signal may be assumed to be analogous to the DQS signal used for enabling exchange of data between the DDR SDRAM and the driving circuit thereof.
As explained herein, the driving circuit may be implemented as an ASIC, which is susceptible to variation in operating environment, such as operating temperature, operating voltage and the like, thereof. Specifically, due to variation in the operating environment thereof by factors such as Process variation, Voltage variation and Temperature variation (collectively referred to as “PVT considerations”), the ASIC may not be able to meet the timing specifications of the SDRAM interfaced thereto. For example, upon variation of an ambient temperature in the vicinity of the ASIC, a DQS signal of a DDR SDRAM may be required to be appropriately delayed by the ASIC to prevent exchange of erroneous data between the ASIC and the DDR SDRAM. Accordingly, there is a requirement to tune the control signals, such as the DQS signal, in a manner such that the ASIC is adaptable to variations in the operating environment thereof. Specifically, there is a requirement to delay the control signals appropriately upon encountering changes in operating environment of the ASIC due to PVT considerations. Various techniques are known in the art to tune the control signal. One such technique involves utilization of a Digital Delay Line (DDL) for delaying the control signals digitally upon determining variation in the operating environment of the ASIC. However, known implementations of the DDL utilize a single setting to tune the control signal. Specifically, the single setting is obtained during characterization phase of the ASIC during which the ASIC is subjected to a particular range of temperature and voltage variations only. Such implementations of the DDL are not adapted to tune the control signal for real-time variations in operating environment of the ASIC. Accordingly, the ASIC is non-adaptive to real-time variations in operating environment.
Based on the foregoing, there is a need to tune control signals associated with data exchange process between an ASIC and at least one SDRAM in a manner to appropriately account for variations in operating environment of the ASIC. Specifically, there exists a need for a method for tuning a control signal associated with at least one SDRAM such that the method is adapted to account for real-time variations in operating environment of the ASIC.